The present invention relates to a method for fabricating bipolar-MOS (metal oxide semiconductor) devices. More specifically, it relates to a method to simultaneously fabricate the contact electrodes for each of the bipolar and MOS transistors in a bipolar-MOS device, thus simplifying the fabrication process. The present invention improves the size and the operation speed of the devices when compared to prior art devices fabricated with the same design.
A bipolar-MOS device is a semiconductor device which includes bipolar and MOS devices in a single semiconductor chip. It is often abbreviated as a Bi-MOS device in the art. An exemplar Bi-MOS device is shown in FIG. 1. The figure shows schematically a cross sectional view of a bipolar-MOS device having an n-channel MOS transistor (abbreviated as n-MOS hereinafter), a p channel MOS transistor 2 (abbreviated as p-MOS hereinafter) and an npn type bipolar transistor 3. In the prior art bipolar-MOS device, the FETs and the bipolar transistors are all fabricated in a substrate. More precisely, as can be seen in FIG. 1, they are fabricated in an expitaxial layer 4 formed on a substrate 5.
However, in the prior art configuration, parasitic capacitances are inevitably added to each of the pn junctions of the active regions such as the source S, drain D, emitter E, base B and so on. Therefore, no matter how small the devices are fabricated, it was impossible to increase the operation speed of these devices beyond a certain limiting value.
There are some proposals to increase the operation speed of FETs or bipolar transistors by decreasing the parasitic capacitances. For example, in a document of "A New Buried-Oxide Isolation for High-Speed High-Density MOS Integrated Circuits" by J. Sakurai, pp. 468-471, vol SC-13, No. 4, August 1978, IEEE is disclosed an FET which is fabricated in a selectively grown silicon single crystal over the substrate. The source, drain regions and their contact regions are formed over a thick silicon dioxide layer.
FIG. 2 illustrates a structure of such a FET. As can be seen in the figure, the FET is formed in a single crystal 6 formed over the substrate 5 in an opening of the field oxide layer 7. The contact regions 8 and 9, respectively for the source and the drain, are fabricated on the field oxide layer 7. By using this configuration, the stray capacitances of the pn junctions under these electrodes are reduced. Therefore, not only is the space factor of the device improved, but also the operation speed of the device is increased more than those of the prior art structures.
Recently, there is an increased demand for high speed and high density Bi-MOS devices. Therefore, an important problem arose on how to fabricate the above proposed devices combined in a single IC chip.